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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002
PMADDWD
Packed Multiply Words and Add Doublewords
Multiplies each packed 16-bit signed value in the first source operand by the
corresponding packed 16-bit signed value in the second source operand, adds the
adjacent intermediate 32-bit results of each multiplication (for example, the
multiplication results for the adjacent bit fields 63–48 and 47–32, and 31–16 and
15–0), and writes the 32-bit result of each addition in the corresponding doubleword of
the destination (first source). The first source/destination operand is an XMM register
and the second source operand is another XMM register or 128-bit memory location.
Mnemonic Opcode Description
PMADDWD xmm1, xmm2/mem128 66 0F F5 /r Multiplies eight packed 16-bit signed values in an XMM
register and another XMM register or 128-bit memory
location, adds intermediate results, and writes the result in
the destination XMM register.
xmm1
xmm2/mem128
127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0
127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0
.
. . .
.
. . .
multiply
multiply
multiply
multiply
add
add
.
.
127 96 95 64 63 32 31
0
pmaddwd-128.eps
There is only one case in which the result of the multiplication and addition will not fit
in a signed 32-bit destination. If all four of the 16-bit source operands used to produce
a 32-bit multiply-add result have the value 8000h, the 32-bit result is 8000_0000h,
which is incorrect.
252 PMADDWD