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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The FXSAVE/FSRSTOR instructions are not supported, as indicated by bit 24 of CPUID standard funcion 1 or extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X X A null data segment was used to reference memory. The destination operand was in a non-writable segment. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 116 FXSAVE
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology LDMXCSR Load MXCSR Control/Status Register Loads the MXCSR register with a 32-bit value from memory. The least-significant bit of the memory location is loaded in bit 0 of MXCSR. Bits 31–16 of the MXCSR are reserved and must be zero. A general-protection exception occurs if the LDMXCSR instruction attempts to load non-zero values into MXCSR bits 31–16. The MXCSR register is described in “Registers” in Volume 1. Mnemonic Opcode Description LDMXCSR mem32 0F AE /2 Loads MXCSR register with 32-bit value in memory. Related Instructions STMXCSR rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M M M M M M M M M M M M M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. LDMXCSR 117
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