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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 xmm1 127 64 63 0 xmm2 127 64 63 0 copy xmm1 mem64 127 0 64 63 0 63 0 copy mem64 xmm2 63 0 127 64 63 0 copy movsd.eps This MOVSD instruction should not be confused with the same-mnemonic MOVSD (move string doubleword) instruction in the general-purpose instruction set. Assemblers can distinguish the instructions by the number and type of operands. Related Instructions MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVUPD rFLAGS Affected None. MXCSR Flags Affected None. 180 MOVSD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. MOVSD 181
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