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AMD 64-Bit Technology - ECE User Home Pages

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<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong> 26568—Rev. 3.02—August 2002<br />

DIVSD<br />

Divide Scalar Double-Precision Floating-Point<br />

Divides the double-precision floating-point value in the low-order quadword of the<br />

first source operand by the double-precision floating-point value in the low-order<br />

quadword of the second source operand and writes the result in the low-order<br />

quadword of the destination (first source). The high-order quadword of the<br />

destination is not modified. The first source/destination operand is an XMM register.<br />

The second source operand is another XMM register or 128-bit memory location.<br />

Mnemonic Opcode Description<br />

DIVSD xmm1, xmm2/mem<strong>64</strong> F2 0F 5E /r Divides low-order double-precision floating-point value in an XMM<br />

register by the low-order double-precision floating-point value in<br />

another XMM register or in a <strong>64</strong>- or 128-bit memory location.<br />

xmm1<br />

xmm2/mem<strong>64</strong><br />

127 <strong>64</strong> 63 0 127 <strong>64</strong> 63 0<br />

divide<br />

divsd.eps<br />

Related Instructions<br />

DIVPD, DIVPS, DIVSS<br />

rFLAGS Affected<br />

None<br />

MXCSR Flags Affected<br />

FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE<br />

M M M M M M<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Note:<br />

A flag that can be set to one or zero is M (modified). Unaffected flags are blank.<br />

108 DIVSD

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