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AMD 64-Bit Technology - ECE User Home Pages

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26568—Rev. 3.02—August 2002<br />

<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong><br />

MASKMOVDQU<br />

Masked Move Double Quadword Unaligned<br />

Stores bytes from the first source operand as selected by the sign bits in the second<br />

source operand (sign-bit is 0 = no write and sign-bit is 1 = write) to a memory location<br />

specified in the DS:rDI registers. The first source operand is an XMM register, and the<br />

second source operand is another XMM register. The store address may be unaligned.<br />

Mnemonic Opcode Description<br />

MASKMOVDQU xmm1, xmm2 66 0F F7 /r Store bytes from an XMM register selected by a mask value in<br />

another XMM register to DS:rDI.<br />

xmm1<br />

127 0<br />

xmm2/mem128<br />

127 0<br />

. . . . . . .<br />

select<br />

. . . . . . .<br />

. . . . . . .<br />

. . . . . . .<br />

. . . . . . .<br />

select<br />

. . . . . . .<br />

Memory<br />

store address<br />

DS:rDI<br />

maskmovdqu.eps<br />

A mask value of all 0s results in the following behavior:<br />

„ No data is written to memory.<br />

„ Code and data breakpoints are not guaranteed to be signaled in all implementations.<br />

„ Exceptions associated with memory addressing and page faults are not guaranteed<br />

to be signaled in all implementations.<br />

„ The protection features of memory regions mapped as UC or WP are not guaranteed<br />

to be enforced in all implementations.<br />

MASKMOVDQU 119

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