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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions FWAIT, FXSAVE rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M M M M M M M M M M M M M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The FXSAVE/FSRSTOR instructions are not supported, as indicated by bit 24 of CPUID standard funcion 1 or extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. X X X Ones were written to the reserved bits in MXCSR. Page fault, #PF X X A page fault resulted from the execution of the instruction. 114 FXRSTOR
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology FXSAVE Save XMM, MMX, and x87 State Saves the XMM, MMX, and x87 state. A memory location that is not aligned on a 16- byte boundary causes a general-protection exception. Unlike FSAVE and FNSAVE, FXSAVE does not alter the x87 tag bits. The contents of the saved MMX/x87 data registers are retained, thus indicating that the registers may be valid (or whatever other value the x87 tag bits indicated prior to the save). To invalidate the contents of the MMX/x87 data registers after FXSAVE, software must execute an FINIT instruction. Also, FXSAVE (like FNSAVE) does not check for pending unmasked x87 floating-point exceptions. An FWAIT instruction can be used for this purpose. FXSAVE does not save the x87 pointer registers (last instruction pointer, last data pointer, and last opcode), except in the relatively rare cases in which the exceptionsummary (ES) bit in the x87 status word is set to 1, indicating that an unmasked x87 exception has occurred. The architecture supports two memory formats for FXSAVE, a 512-byte 32-bit legacy format and a 512-byte 64-bit format. Selection of the 32-bit or 64-bit format is accomplished by using the corresponding effective operand size in the FXSAVE instruction. If software running in 64-bit mode executes an FXSAVE with a 32-bit operand size (no REX-prefix operand-size override), the 32-bit legacy format is used. If software running in 64-bit mode executes an FXSAVE with a 64-bit operand size (requires REX-prefix operand-size override), the 64-bit format is used. For details about the memory image restored by FXRSTOR, see “Saving Media and x87 Processor State” in Volume 2. If the operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0, FXSAVE does not save the image of XMM0–XMM7 or MXCSR. For details about the CR4.OSFXSR bit, see “FXSAVE/FXRSTOR Support (OSFXSR) Bit” in Volume 2. Mnemonic Opcode Description FXSAVE mem512env 0F AE /0 Saves XMM, MMX, and x87 state to 512-byte memory location. Related Instructions FINIT, FNSAVE, FRSTOR, FSAVE, FXRSTOR, LDMXCSR, STMXCSR FXSAVE 115
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