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AMD 64-Bit Technology - ECE User Home Pages

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26568—Rev. 3.02—August 2002<br />

<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong><br />

MAXPD<br />

Maximum Packed Double-Precision Floating-<br />

Point<br />

Compares each of the two packed double-precision floating-point values in the first<br />

source operand with the corresponding packed double-precision floating-point value<br />

in the second source operand and writes the numerically greater of the two values for<br />

each comparison in the corresponding quadword of the destination (first source). The<br />

first source/destination operand is an XMM register. The second source operand is<br />

another XMM register or 128-bit memory location.<br />

Mnemonic Opcode Description<br />

MAXPD xmm1, xmm2/mem128 66 0F 5F /r Compares two pairs of packed double-precision values in an<br />

XMM register and another XMM register or 128-bit memory<br />

location and writes the greater value of each comparison in the<br />

destination XMM register.<br />

xmm1<br />

xmm2/mem128<br />

127 <strong>64</strong> 63 0 127 <strong>64</strong> 63 0<br />

maximum<br />

maximum<br />

maxpd.eps<br />

If both source operands are equal to zero, the value in the second source operand is<br />

returned. If either operand is a NaN (SNaN or QNaN), and invalid-operation<br />

exceptions are masked, the second source operand is written to the destination.<br />

Related Instructions<br />

MAXPS, MAXSD, MAXSS, MINPD, MINPS, MINSD, MINSS<br />

rFLAGS Affected<br />

None<br />

MAXPD 121

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