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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Definitions This volume describes the 128-bit media instructions. The index at the end cross-references topics within this volume. For other topics relating to the x86-64 architecture, and for information on instructions in other subsets, see the tables of contents and indexes of the other volumes. Many of the following definitions assume an in-depth knowledge of the legacy x86 architecture. See “Related Documents” on page xxiii for descriptions of the legacy x86 architecture. Terms and Notation In addition to the notation described below, “Opcode-Syntax Notation” in Volume 3 describes notation relating specifically to opcodes. 1011b A binary value—in this example, a 4-bit value. F0EAh A hexadecimal value—in this example a 2-byte value. [1,2) A range that includes the left-most value (in this case, 1) but excludes the right-most value (in this case, 2). 7–4 A bit range, from bit 7 to 4, inclusive. The high-order bit is shown first. 128-bit media instructions Instructions that use the 128-bit XMM registers. These are a combination of the SSE and SSE2 instruction sets. 64-bit media instructions Instructions that use the 64-bit MMX registers. These are primarily a combination of MMX and 3DNow! instruction sets, with some additional instructions from the SSE and SSE2 instruction sets. 16-bit mode Legacy mode or compatibility mode in which a 16-bit address size is active. See legacy mode and compatibility mode. xii Preface
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology 32-bit mode Legacy mode or compatibility mode in which a 32-bit address size is active. See legacy mode and compatibility mode. 64-bit mode A submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, such as register extensions, are supported for system and application software. #GP(0) Notation indicating a general-protection exception (#GP) with error code of 0. absolute Said of a displacement that references the base of a code segment rather than an instruction pointer. Contrast with relative. biased exponent The sum of a floating-point value’s exponent and a constant bias for a particular floating-point data type. The bias makes the range of the biased exponent always positive, which allows reciprocation without overflow. byte Eight bits. clear To write a bit value of 0. Compare set. compatibility mode A submode of long mode. In compatibility mode, the default address size is 32 bits, and legacy 16-bit and 32-bit applications run without modification. commit To irreversibly write, in program order, an instruction’s result to software-visible storage, such as a register (including flags), the data cache, an internal write buffer, or memory. CPL Current privilege level. Preface xiii
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