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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Real Virtual 8086 Protected Cause of Exception Underflow exception (UE) X X X A rounded result was too small to fit into the format of the destination operand. Denormalized-operand X X X A source operand was a denormal value. exception (DE) Precision exception (PE) X X X A result could not be represented exactly in the destination format. 194 MULPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MULSD Multiply Scalar Double-Precision Floating-Point Multiplies the double-precision floating-point value in the low-order quadword of first source operand by the double-precision floating-point value in the low-order quadword of the second source operand and writes the result in the low-order quadword of the destination (first source). The high-order quadword of the destination is not modified. The first source/destination operand is an XMM register. The second source operand is another XMM register or 64-bit memory location. Mnemonic Opcode Description MULSD xmm1, xmm2/mem64 F2 0F 59 /r Multiplies low-order double-precision floating-point values in an XMM register and another XMM register or 64-bit memory location and writes the result in the low-order quadword of the destination XMM register. xmm1 xmm2/mem64 127 64 63 0 127 64 63 0 multiply mulsd.eps Related Instructions MULPD, MULPS, MULSS, PFMUL rFLAGS Affected None MULSD 195
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