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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 SQRTSD Square Root Scalar Double-Precision Floating-Point Computes the square root of the low-order double-precision floating-point value in an XMM register or in a 64-bit memory location and writes the result in the low-order quadword of another XMM register. The high-order quadword of the destination XMM register is not modified. Taking the square root of +infinity returns +infinity. Mnemonic Opcode Description SQRTSD xmm1, xmm2/mem64 F2 0F 51 /r Computes square root of double-precision floating-point value in an XMM register or 64-bit memory location and writes the result in the destination XMM register. xmm1 xmm2/mem64 127 64 63 0 127 64 63 0 square root sqrtsd.eps Related Instructions RSQRTPS, RSQRTSS, SQRTPD, SQRTPS, SQRTSS rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. 362 SQRTSD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions. Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point Exception, #XF Invalid-operation exception (IE) X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions X X X X X X A source operand was an SNaN value. A source operand was negative (not including –0). Denormalized-operand X X X A source operand was a denormal value. exception (DE) Precision exception (PE) X X X A result could not be represented exactly in the destination format. SQRTSD 363
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