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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 CVTTSD2SI Convert Scalar Double-Precision Floating-Point to Signed Doubleword of Quadword Integer, Truncated Converts a double-precision floating-point value in the low-order 64 bits of an XMM register or a 64-bit memory location to a 32-bit or 64-bit signed integer value and writes the converted value in a general-purpose register. Mnemonic Opcode Description CVTTSD2SI reg32, xmm/mem64 F2 0F 2C /r Converts scalar double-precision floating-point value in an XMM register or 64-bit memory location to a doubleword signed integer value in a general-purpose register. Inexact results are truncated. CVTTSD2SI reg64, xmm/mem64 F2 0F 2C /r Converts scalar double-precision floating-point value in an XMM register or 64-bit memory location to a quadword signed integer value in a general-purpose register. Inexact results are truncated. reg32 xmm2/mem64 31 0 127 64 63 0 convert reg64 xmm2/mem64 63 0 127 64 63 0 convert with REX prefix cvttsd2si.eps If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 – 1) or quadword value (–2 63 to +2 63 – 1), the instruction returns the indefinite integer value 96 CVTTSD2SI
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology (8000_0000h for 32-bit integers, 8000_0000_0000_0000h for 64-bit integers) when the invalid-operation exception (IE) is masked. Related Instructions CVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. CVTTSD2SI 97
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