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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PSADBW Packed Sum of Absolute Differences of Bytes Into a Word Computes the absolute differences of eight corresponding packed 8-bit unsigned integers in the first and second source operands and writes the unsigned 16-bit integer result of the sum of the eight differences in a word in the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PSADBW xmm1, xmm2/mem128 66 0F F6 /r Compute the sum of the absolute differences of two sets of packed 8-bit unsigned integer values in an XMM register and another XMM register or 128-bit memory location and writes the 16-bit unsigned integer result in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 64 63 0 . . . . . . . . . . . . . . . . . . . . . . . . absolute difference absolute difference add 8 pairs absolute difference absolute difference add 8 pairs 127 79 64 63 15 0 0 0 psadbw-128.eps The sum of the differences of the eight bytes in the high-order quadwords of the source operands are written in the least-significant word of the high-order quadword in the destination XMM register, with the remaining bytes cleared to all 0s. The sum of 274 PSADBW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology the differences of the eight bytes in the low-order quadwords of the source operands are written in the least-significant word of the low-order quadword in the destination XMM register, with the remaining bytes cleared to all 0s. rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X X Virtual 8086 Protected Cause of Exception X X X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1; and the AMD extensions to MMX are not supported, as indicated by bit 22 of CPUID extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PSADBW 275
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