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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM General protection X The destination operand was in a non-writable segment. x87 floating-point exception pending, #MF X X X An exception was pending due to an x87 floating-point instruction. 148 MOVDQ2Q
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVDQA Move Aligned Double Quadword Moves an aligned 128-bit (double quadword) value: „ from an XMM register or 128-bit memory location to another XMM register, or „ from an XMM register to a 128-bit memory location or another XMM register. Mnemonic Opcode Description MOVDQA xmm1, xmm2/mem128 66 0F 6F /r Moves 128-bit value from an XMM register or 128-bit memory location to the destination XMM register. MOVDQA xmm1/mem128, xmm2 66 0F 7F /r Moves 128-bit value from an XMM register to the destination XMM register or 128-bit memory location. xmm1 127 0 xmm2/mem128 127 0 copy xmm1/mem128 127 0 xmm2 127 0 copy movdqa.eps A memory operand that is not aligned on a 16-byte boundary causes a generalprotection exception. Related Instructions MOVD, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQ rFLAGS Affected None MOVDQA 149
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