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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 236 PCMPEQB
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PCMPEQD Packed Compare Equal Doublewords Compares corresponding packed 32-bit values in the first and second source operands and writes the result of each comparison in the corresponding 32 bits of the destination (first source). For each pair of doublewords, if the values are equal, the result is all 1s. If the values are not equal, the result is all 0s. The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PCMPEQD xmm1, xmm2/mem128 66 0F 76 /r Compares packed doublewords in an XMM register and an XMM register or 128-bit memory location. xmm1 . . 127 96 95 64 63 32 31 0 xmm2/mem128 127 96 95 64 63 32 31 0 compare all 1s or 0s . . compare all 1s or 0s . . pcmpeqd-128.eps Related Instructions PCMPEQB, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW rFLAGS Affected None MXCSR Flags Affected None PCMPEQD 237
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