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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions PSLLD, PSLLDQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 290 PSLLQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PSLLW Packed Shift Left Logical Words Left-shifts each of the packed 16-bit values in the first source operand by the number of bits specified in the second source operand and writes each shifted value in the corresponding word of the destination (first source). The first source/destination and second source operands are: „ an XMM register and another XMM register or 128-bit memory location, or „ an XMM register and an immediate byte value The low-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greater than 15, the destination is cleared to all 0s. Mnemonic Opcode Description PSLLW xmm1, xmm2/mem128 66 0F F1 /r Left-shifts packed words in an XMM register by the amount specified in the low 64 bits of an XMM register or 128-bit memory location. PSLLW xmm, imm8 66 0F 71 /6 ib Left-shifts packed words in an XMM register by the amount specified in an immediate byte value. xmm1 . . . . . . xmm2/mem128 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 127 64 63 0 shift left . . . . . . shift left xmm . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 imm8 7 0 shift left . . . . . . shift left psllw-128.eps PSLLW 291
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