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AMD 64-Bit Technology - ECE User Home Pages

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26568—Rev. 3.02—August 2002<br />

<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong><br />

CVTPD2PI<br />

Convert Packed Double-Precision Floating-Point<br />

to Packed Doubleword Integers<br />

Converts two packed double-precision floating-point values in an XMM register or a<br />

128-bit memory location to two packed 32-bit signed integer values and writes the<br />

converted values in an MMX register.<br />

Mnemonic Opcode Description<br />

CVTPD2PI mmx, xmm2/mem128 66 0F 2D /r Converts packed double-precision floating-point values in an<br />

XMM register or 128-bit memory location to packed<br />

doubleword integers values in the destination MMX register.<br />

mmx<br />

xmm/mem128<br />

63 32 31 0<br />

127 <strong>64</strong> 63 0<br />

convert<br />

convert<br />

cvtpd2pi.eps<br />

If the result of the conversion is an inexact value, the value is rounded as specified by<br />

the rounding control bits (RC) in the MXCSR register. If the floating-point value is a<br />

NaN, infinity, or if the result of the conversion is larger than the maximum signed<br />

doubleword (–2 31 to +2 31 – 1), the instruction returns the 32-bit indefinite integer<br />

value (8000_0000h) when the invalid-operation exception (IE) is masked.<br />

Execution of this instruction causes all fields in the x87 tag word to be set according to<br />

their corresponding data, the top-of-stack-pointer bit (TOP) in the x87 status word to<br />

be cleared to 0, and any pending x87 exceptions are handled before this instruction is<br />

executed. For details, see “Actions Taken on Executing <strong>64</strong>-<strong>Bit</strong> Media Instructions” in<br />

Volume 1.<br />

Related Instructions<br />

CVTDQ2PD, CVTPD2DQ, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ,<br />

CVTTPD2PI, CVTTSD2SI<br />

CVTPD2PI 49

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