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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PUNPCKHBW Unpack and Interleave High Bytes Unpacks the high-order bytes from the first and second source operands and packs them into interleaved-byte words in the destination (first source). The low-order bytes of the source operands are ignored. The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PUNPCKHBW xmm1, xmm2/mem128 66 0F 68 /r Unpacks the eight high-order bytes in an XMM register and another XMM register or 128-bit memory location and packs them into interleaved bytes in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 64 63 0 . . . . . . copy copy copy . . . . . . copy . . . . . . . . . . . . 127 64 63 0 punpckhbw-128.eps If the second source operand is all 0s, the destination contains the bytes from the first source operand zero-extended to 16 bits. This operation is useful for expanding unsigned 8-bit values to unsigned 16-bit operands for subsequent processing that requires higher precision. Related Instructions PUNPCKHDQ, PUNPCKHQDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLQDQ, PUNPCKLWD rFLAGS Affected None 324 PUNPCKHBW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PUNPCKHBW 325
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