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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 286 PSLLD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PSLLDQ Packed Shift Left Logical Double Quadword Left-shifts the 128-bit (double quadword) value in an XMM register by the number of bytes specified in an immediate byte value. The low-order bytes that are emptied by the shift operation are cleared to 0. If the shift value is greater than 15, the destination XMM register is cleared to all 0s. Mnemonic Opcode Description PSLLDQ xmm, imm8 66 0F 73 /7 ib Left-shifts double quadword value in an XMM register by the amount specified in an immediate byte value. xmm 127 0 imm8 7 0 shift left pslldq.eps Related Instructions PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW rFLAGS Affected None MXCSR Flags Affected None PSLLDQ 287
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