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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 „ Web sites and newsgroups: - www.amd.com - news.comp.arch - news.comp.lang.asm.x86 - news.intel.microprocessors - news.microsoft xxvi Preface
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology 1 128-Bit Media Instruction Reference This chapter describes the function, mnemonic syntax, opcodes, affected flags of the 128-bit media instructions and the possible exceptions they generate. These instructions load, store, or operate on data located in 128-bit XMM registers. Most of the instructions operate in parallel on sets of packed elements called vectors, although a few operate on scalars. These instructions define both integer and floating-point operations. They include the legacy SSE and SSE2 instructions. Each instruction that performs a vector (packed) operation is illustrated with a diagram. Figure 1-1 on page 2 shows the conventions used in these diagrams. The particular diagram shows the PSLLW (packed shift left logical words) instruction. 1
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