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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions PINSRW rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1; and the AMD extensions to MMX are not supported, as indicated by bit 22 of CPUID extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. 248 PEXTRW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PINSRW Packed Insert Word Inserts a 16-bit value from the low-order word of a 32-bit general purpose register or a 16-bit memory location into an XMM register. The location in the destination register is selected by the immediate byte operand, as shown in Table 1-3. The other words in the destination register operand are not modified. Mnemonic Opcode Description PINSRW xmm, reg32/mem16, imm8 66 0F C4 /r ib Inserts a 16-bit value from a general-purpose register or memory location into an XMM register. xmm reg32/mem16 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 32 15 0 imm8 7 0 select word position for insert pinsrw-128.eps PINSRW 249
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