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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. Device not available, #NM x87 floating-point exception pending, #MF X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. X X X An exception was pending due to an x87 floating-point instruction. 178 MOVQ2DQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVSD Move Scalar Double-Precision Floating-Point Moves a scalar double-precision floating-point value: „ from the low-order 64 bits of an XMM register or a 64-bit memory location to the low-order 64 bits of another XMM register, or „ from the low-order 64 bits of an XMM register to the low-order 64 bits of another XMM register or a 64-bit memory location. If the source operand is an XMM register, the high-order 64 bits of the destination XMM register are not modified. If the source operand is a memory location, the highorder 64 bits of the destination XMM register are cleared to all 0s. Mnemonic Opcode Description MOVSD xmm1, xmm2/mem64 F2 0F 10 /r Moves double-precision floating-point value from an XMM register or 64-bit memory location to an XMM register. MOVSD xmm1/mem64, xmm2 F2 0F 11 /r Moves double-precision floating-point value from an XMM register to an XMM register or 64-bit memory location. MOVSD 179
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