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AMD 64-Bit Technology - ECE User Home Pages

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<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong> 26568—Rev. 3.02—August 2002<br />

PUNPCKHWD<br />

Unpack and Interleave High Words<br />

Unpacks the high-order words from the first and second source operands and packs<br />

them into interleaved-word doublewords in the destination (first source). The loworder<br />

words of the source operands are ignored. The first source/destination operand<br />

is an XMM register and the second source operand is another XMM register or 128-bit<br />

memory location.<br />

Mnemonic Opcode Description<br />

PUNPCKHWD xmm1, xmm2/mem128 66 0F 69 /r Unpacks four high-order words in an XMM register and<br />

another XMM register or 128-bit memory location and packs<br />

them into interleaved words in the destination XMM<br />

register.<br />

xmm1<br />

127 112 111 96 95 80 79 <strong>64</strong> 63 0<br />

xmm2/mem128<br />

127 112 111 96 95 80 79 <strong>64</strong> 63 0<br />

. .<br />

copy<br />

copy<br />

copy<br />

. .<br />

copy<br />

. . . .<br />

. . . . . . . . . . . .<br />

127 112 111 96 95 80 79 <strong>64</strong> 63 48 47 32 31 16 15 0<br />

punpckhwd-128.eps<br />

If the second source operand is all 0s, the destination contains the words from the first<br />

source operand zero-extended to 32 bits. This operation is useful for expanding<br />

unsigned 16-bit values to unsigned 32-bit operands for subsequent processing that<br />

requires higher precision.<br />

Related Instructions<br />

PUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKLBW, PUNPCKLDQ,<br />

PUNPCKLQDQ, PUNPCKLWD<br />

330 PUNPCKHWD

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