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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Invalid-operation exception (IE) Real X Virtual 8086 Protected Cause of Exception X SIMD Floating-Point Exceptions X A source operand was an SNaN value, a QNaN value, or ±infinity. X X X A source operand was too large to fit in the destination format. Precision exception (PE) X X X A result could not be represented exactly in the destination format. 86 CVTTPD2DQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CVTTPD2PI Convert Packed Double-Precision Floating-Point to Packed Doubleword Integers, Truncated Converts two packed double-precision floating-point values in an XMM register or a 128-bit memory location to two packed 32-bit signed integer values and writes the converted values in an MMX register. Mnemonic Opcode Description CVTPD2PI mmx, xmm/mem128 66 0F 2C /r Converts packed double-precision floating-point values in an XMM register or 128-bit memory location to packed doubleword integer values in the destination MMX register. Inexact results are truncated. mmx xmm/mem128 63 32 31 0 127 64 63 0 convert convert cvttpd2pi.eps If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 – 1), the instruction returns the 32-bit indefinite integer value (8000_0000h) when the invalidoperation exception (IE) is masked. Related Instructions CVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTSD2SI rFLAGS Affected None CVTTPD2PI 87
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