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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Memory operands that are not aligned on a 16-byte boundary do not cause a generalprotection exception. Related Instructions MOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned-memory reference was performed while alignment checking was enabled. 188 MOVUPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MULPD Multiply Packed Double-Precision Floating- Point Multiplies each of the two packed double-precision floating-point values in the first source operand by the corresponding packed double-precision floating-point value in the second source operand and writes the result of each multiplication operation in the corresponding quadword of the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description MULPD xmm1, xmm2/mem128 66 0F 59 /r Multiplies packed double-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and writes the results in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 64 63 0 multiply multiply mulpd.eps Related Instructions MULPS, MULSD, MULSS, PFMUL rFLAGS Affected None MULPD 189
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