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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 COMISD Compare Ordered Scalar Double-Precision Floating-Point Compares the double-precision floating-point value in the low-order 64 bits of an XMM register with the double-precision floating-point value in the low-order 64 bits of another XMM register or a 64-bit memory location and sets the ZF, PF, and CF bits in the rFLAGS register to reflect the result of the comparison. The result is unordered if one or both of the operand values is a NaN. The OF, AF, and SF bits in rFLAGS are set to zero. If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated. Mnemonic Opcode Description COMISD xmm1, xmm2/mem64 66 0F 2F /r Compares double-precision floating-point values in an XMM register and an XMM register or 64-bit memory location and sets rFLAGS. xmm1 127 64 63 0 xmm2/mem64 127 64 63 0 compare 63 0 31 rFLAGS 0 comisd.eps Result of Compare ZF PF CF Unordered 1 1 1 Greater Than 0 0 0 Less Than 0 0 1 Equal 1 0 0 36 COMISD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Related Instructions CMPPD, CMPPS, CMPSD, CMPSS, COMISS, UCOMISD, UCOMISS rFLAGS Affected ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF MXCSR Flags Affected 0 0 M 0 M M 21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0 Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated. FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. COMISD 37
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