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AMD 64-Bit Technology - ECE User Home Pages

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<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong> 26568—Rev. 3.02—August 2002<br />

PUNPCKLDQ<br />

Unpack and Interleave Low Doublewords<br />

Unpacks the low-order doublewords from the first and second source operands and<br />

packs them into interleaved-doubleword quadwords in the destination (first source).<br />

The high-order doublewords of the source operands are ignored. The first<br />

source/destination operand is an XMM register and the second source operand is<br />

another XMM register or 128-bit memory location.<br />

Mnemonic Opcode Description<br />

PUNPCKLDQ xmm1, xmm2/mem128 66 0F 62 /r Unpacks two low-order doublewords in an XMM register and<br />

another XMM register or 128-bit memory location and packs<br />

them into interleaved doublewords in the destination XMM<br />

register.<br />

xmm1<br />

127 <strong>64</strong> 63 32 31<br />

0<br />

xmm2/mem128<br />

127 <strong>64</strong> 63 32 31<br />

0<br />

copy<br />

copy<br />

copy<br />

copy<br />

127 96 95 <strong>64</strong> 63 32 31<br />

0<br />

punpckldq-128.eps<br />

If the second source operand is all 0s, the destination contains the doubleword(s) from<br />

the first source operand zero-extended to <strong>64</strong> bits. This operation is useful for<br />

expanding unsigned 32-bit values to unsigned <strong>64</strong>-bit operands for subsequent<br />

processing that requires higher precision.<br />

Related Instructions<br />

PUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKHWD, PUNPCKLBW,<br />

PUNPCKLQDQ, PUNPCKLWD<br />

334 PUNPCKLDQ

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