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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. 288 PSLLDQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PSLLQ Packed Shift Left Logical Quadwords Left-shifts each 64-bit value in the first source operand by the number of bits specified in the second source operand and writes each shifted value in the corresponding quadword of the destination (first source). The first source/destination and second source operands are: „ an XMM register and another XMM register or 128-bit memory location, or „ an XMM register and an immediate byte value. The low-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greater than 63, the destination is cleared to all 0s. Mnemonic Opcode Description PSLLQ xmm1, xmm2/mem128 66 0F F3 /r Left-shifts packed quadwords in XMM register by the amount specified in the low 64 bits of an XMM register or 128-bit memory location. PSLLQ xmm, imm8 66 0F 73 /6 ib Left-shifts packed quadwords in an XMM register by the amount specified in an immediate byte value. xmm1 127 64 63 0 xmm2/mem128 127 64 63 0 shift left shift left xmm imm8 127 64 63 0 7 0 shift left shift left psllq-128.eps PSLLQ 289
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