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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Real Virtual 8086 Protected Cause of Exception Overflow exception (OE) X X X A rounded result was too large to fit into the format of the destination operand. Underflow exception (UE) X X X A rounded result was too small to fit into the format of the destination operand. Denormalized-operand X X X A source operand was a denormal value. exception (DE) Zero-divide exception (ZE) X X X A non-zero number was divided by zero. Precision exception (PE) X X X A result could not be represented exactly in the destination format. 104 DIVPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology DIVPS Divide Packed Single-Precision Floating-Point Divides each of the four packed single-precision floating-point values in the first source operand by the corresponding packed single-precision floating-point value in the second source operand and writes the result of each division in the corresponding quadword of the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description DIVPS xmm1, xmm2mem/128 0F 5E /r Divides packed single-precision floating-point values in an XMM register by the packed single-precision floating-point values in another XMM register or 128-bit memory location. xmm1 xmm2/mem128 127 96 95 64 63 32 31 0 127 96 95 64 63 32 31 0 divide divide divide divide divps.eps Related Instructions DIVPD, DIVSD, DIVSS rFLAGS Affected None DIVPS 105
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