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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PMOVMSKB Packed Move Mask Byte Moves the most-significant bit of each byte in the source operand to the destination, with zero-extension to 32 bits. The destination and source operands are a 32-bit general-purpose register and an XMM register. The result is written to the low-order word of the general-purpose register. Mnemonic Opcode Description PMOVMSKB reg32, xmm 66 0F D7 /r Moves most-significant bit of each byte in an XMM register to loworder word of a 32-bit general-purpose register. reg32 xmm 32 0 15 . ... . . ..... . . .... 0 127 119 111 103 95 87 79 71 63 55 47 39 31 23 15 7 0 . . . . . . . . . copy . . . . . copy pmovmskb-128.eps Related Instructions MOVMSKPD, MOVMSKPS rFLAGS Affected None MXCSR Flags Affected None 262 PMOVMSKB
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. Device not available, #NM X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. PMOVMSKB 263
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