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AMD 64-Bit Technology - ECE User Home Pages

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26568—Rev. 3.02—August 2002<br />

<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong><br />

PADDW<br />

Packed Add Words<br />

Adds each packed 16-bit integer value in the first source operand to the corresponding<br />

packed 16-bit integer in the second source operand and writes the integer result of<br />

each addition in the corresponding word of the destination (second source). The first<br />

source/destination operand is an XMM register and the second source operand is<br />

another XMM register or 128-bit memory location.<br />

Mnemonic Opcode Description<br />

PADDW xmm1, xmm2/mem128 66 0F FD /r Adds packed 16-bit integer values in an XMM register and<br />

another XMM register or 128-bit memory location and writes<br />

the result in the destination XMM register.<br />

xmm1<br />

. . . . . .<br />

127 112 111 96 95 80 79 <strong>64</strong> 63 48 47 32 31 16 15 0<br />

xmm2/mem128<br />

127 112 111 96 95 80 79 <strong>64</strong> 63 48 47 32 31 16 15 0<br />

. . . . . .<br />

. . . . . .<br />

add<br />

add<br />

paddw-128.eps<br />

This instruction operates on both signed and unsigned integers. If the result<br />

overflows, the carry is ignored (neither the overflow nor carry bit in rFLAGS is set),<br />

and only the low-order 16 bits of the result are written in the destination.<br />

Related Instructions<br />

PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW<br />

rFLAGS Affected<br />

None<br />

MXCSR Flags Affected<br />

None<br />

PADDW 225

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