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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 390 UNPCKHPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology UNPCKLPD Unpack Low Double-Precision Floating-Point Unpacks the low-order double-precision floating-point values in the first and second source operands and packs them into the destination (first source). The value from the first source operand is packed into the low-order quadword of the destination, and the value from the second source operand is packed into the high-order quadword of the destination. The high-order quadwords of the source operands are ignored. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description UNPCKLPD xmm1, xmm2/mem128 66 0F 14 /r Unpacks low-order double-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and packs them into the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 64 63 0 copy copy 127 64 63 0 unpcklpd.eps Related Instructions UNPCKHPD, UNPCKHPS, UNPCKLPS rFLAGS Affected None MXCSR Flags Affected UNPCKLPD 391
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