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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of the control register (CR4) was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. 164 MOVLPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVMSKPD Extract Packed Double-Precision Floating-Point Sign Mask Moves the sign bits of two packed double-precision floating-point values in an XMM register to the two low-order bits of a 32-bit general-purpose register, with zeroextension. Mnemonic Opcode Description MOVMSKPD reg32, xmm 66 0F 50 /r Move sign bits in an XMM register to a 32-bit general-purpose register. reg32 xmm 31 1 0 127 63 0 0 copy sign copy sign movmskpd.eps Related Instructions MOVMSKPS, PMOVMSKB rFLAGS Affected None MXCSR Flags Affected None MOVMSKPD 165
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