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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Invalid-operation exception (IE) Real X X Virtual 8086 Protected Cause of Exception X X SIMD Floating-Point Exceptions X X A source operand was an SNaN value. A source operand was negative (not including –0). Denormalized-operand X X X A source operand was a denormal value. exception (DE) Precision exception (PE) X X X A result could not be represented exactly in the destination format. 366 SQRTSS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology STMXCSR Store MXCSR Control/Status Register Saves the contents of the MXCSR register in a 32-bit location in memory. The MXCSR register is described in “Registers” in Volume 1. Mnemonic Opcode Description STMXCSR mem32 0F AE /3 Stores contents of MXCSR in 32-bit memory location. Related Instructions LDMXCSR rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. STMXCSR 367
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