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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X X A null data segment was used to reference memory. The destination operand was in a non-writable segment. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 150 MOVDQA
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVDQU Move Unaligned Double Quadword Moves an unaligned 128-bit (double quadword) value: „ from an XMM register or 128-bit memory location to another XMM register, or „ from an XMM register to another XMM register or 128-bit memory location. Mnemonic Opcode Description MOVDQU xmm1, xmm2/mem128 F3 0F 6F /r Moves 128-bit value from an XMM register or unaligned 128-bit memory location to the destination XMM register. MOVDQU xmm1/mem128, xmm2 F3 0F 7F /r Moves 128-bit value from an XMM register to the destination XMM register or unaligned 128-bit memory location. xmm1 127 0 xmm2/mem128 127 0 copy xmm1/mem128 127 0 xmm2 127 0 copy movdqu.eps Memory operands that are not aligned on a 16-byte boundary do not cause a generalprotection exception. Related Instructions MOVD, MOVDQA, MOVDQ2Q, MOVQ, MOVQ2DQ rFLAGS Affected None MOVDQU 151
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