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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Real Virtual 8086 Protected Cause of Exception Underflow exception (UE) X X X A rounded result was too small to fit into the format of the destination operand. Denormalized-operand X X X A source operand was a denormal value. exception (DE) Precision exception (PE) X X X A result could not be represented exactly in the destination format. 72 CVTSD2SS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CVTSI2SD Convert Signed Doubleword or Quadword Integer to Scalar Double-Precision Floating- Point Converts a 32-bit or 64-bit signed integer value in a general-purpose register or memory location to a double-precision floating-point value and writes the converted value in the low-order 64 bits of an XMM register. The high-order 64 bits in the destination XMM register are not modified. Mnemonic Opcode Description CVTSI2SD xmm, reg/mem32 F2 0F 2A /r Converts a doubleword integer in a general-purpose register or 32- bit memory location to a double-precision floating-point value in the destination XMM register. CVTSI2SD xmm, reg/mem64 F2 0F 2A /r Converts a quadword integer in a general-purpose register or 64-bit memory location to a double-precision floating-point value in the destination XMM register. xmm reg/mem32 127 64 63 0 31 0 convert xmm 127 64 63 0 reg/mem64 63 0 convert with REX prefix cvtsi2sd.eps If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. CVTSI2SD 73
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