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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions MOVHPD, MOVLPD, MOVMSKPD, MOVSD, MOVUPD rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X X A null data segment was used to reference memory. The destination operand was in a non-writable segment. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 140 MOVAPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVAPS Move Aligned Packed Single-Precision Floating-Point Moves four packed single-precision floating-point values: „ from an XMM register or 128-bit memory location to another XMM register, or „ from an XMM register to another XMM register or 128-bit memory location. Mnemonic Opcode Description MOVAPS xmm1, xmm2/mem128 0F 28 /r Moves aligned packed single-precision floating-point value from an XMM register or 128-bit memory location to the destination XMM register. MOVAPS xmm1/mem128, xmm2 0F 29 /r Moves aligned packed single-precision floating-point value from an XMM register to the destination XMM register or 128-bit memory location. MOVAPS 141
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