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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PSHUFLW Packed Shuffle Low Words Moves any one of the four packed words in the low-order quadword of an XMM register or 128-bit memory location to each word in the low-order quadword of another XMM register. In each case, the selection of the value of the destination word is determined by a two-bit field in the immediate-byte operand, with bits 0 and 1 selecting the contents of the low-order word, bits 2 and 3 selecting the second word, bits 4 and 5 selecting the third word, and bits 6 and 7 selecting the high-order word. Refer to Table 1-6 on page 283. A word in the source operand may be copied to more than one word in the destination. The high-order quadword of the source operand is copied to the high-order quadword of the destination register. Mnemonic Opcode Description PSHUFLW xmm1, xmm2/mem128, imm8 F2 0F 70 /r ib Shuffles packed 16-bit values in low-order quadword of an XMM register or 128-bit memory location and puts the result in loworder quadword of another XMM register. xmm1 xmm2/mem128 127 64 63 48 47 32 31 16 15 0 127 64 63 48 47 32 31 16 15 0 imm8 7 0 mux mux mux mux pshuflw.eps 282 PSHUFLW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Table 1-6. Immediate-Byte Operand Encoding for PSHUFLW Destination Bits Filled Immediate-Byte Bit Field Value of Bit Field Source Bits Moved 0 15–0 15–0 1–0 1 31–16 2 47–32 3 63–48 0 15–0 31–16 3–2 1 31–16 2 47–32 3 63–48 0 15–0 47–32 5–4 1 31–16 2 47–32 3 63–48 0 15–0 63–48 7–6 1 31–16 2 47–32 3 63–48 Related Instructions PSHUFD, PSHUFHW, PSHUFW rFLAGS Affected None MXCSR Flags Affected None PSHUFLW 283
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