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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 page 24. When swapping operands, the first source XMM register is overwritten by the result. Related Instructions CMPPD, CMPSD, CMPSS, COMISD, COMISS, UCOMISD, UCOMISS rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. 28 CMPPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exception Page fault, #PF X X A page fault resulted from the execution of the instruction. SIMD Floating-Point Exception, #XF Invalid-operation exception (IE) Denormalized-operand exception (DE) Real X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions X X Virtual 8086 Protected Cause of Exception X X X X A source operand was an SNaN value. A source operand was a QNaN value, and the comparison does not allow QNaN values (refer to Table 1-1 on page 24). X X X A source operand was a denormal value. CMPPS 29
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