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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions MOVDQA, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQ rFLAGS Affected None MXCSR Flags Affected None Exceptions (All Modes) Exception Invalid opcode, #UD Real X Virtual 8086 Protected Description X X The MMX instructions are not supported, as indicated by bit 23 of CPUID standard function 1. X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The instruction used XMM registers while CR4.OSFXSR=0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. Page fault, #PF X X A page fault resulted from the execution of the instruction. x87 floating-point exception pending, #MF X X X An x87 floating-point exception was pending and the instruction referenced an MMX register. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. 146 MOVD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVDQ2Q Move Quadword to Quadword Moves the low-order 64-bit value in an XMM register to a 64-bit MMX register. Mnemonic Opcode Description MOVDQ2Q mmx, xmm F2 0F D6 /r Moves low-order 64-bit value from an XMM register to the destination MMX register. mmx xmm 63 0 127 64 63 0 copy movdq2q.eps Related Instructions MOVD, MOVDQA, MOVDQU, MOVQ, MOVQ2DQ rFLAGS Affected None MXCSR Flags Affected None MOVDQ2Q 147
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