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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Invalid-operation exception (IE) Denormalized-operand exception (DE) Real X X Virtual 8086 Protected Cause of Exception X X SIMD Floating-Point Exceptions X X A source operand was an SNaN value. A source operand was a QNaN value, and the comparison does not allow QNaN values (refer to Table 1-1 on page 24). X X X A source operand was a denormal value. 26 CMPPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CMPPS Compare Packed Single-Precision Floating-Point Compares each of the four packed single-precision floating-point values in the first source operand with the corresponding packed single-precision floating-point value in the second source operand and writes the result of each comparison in the corresponding 32 bits of the destination (first source). The type of comparison is specified by the three low-order bits of the immediate-byte operand, as shown in Table 1-1 on page 24. The result of each compare is a 32-bit value of all 1s (TRUE) or all 0s (FALSE). The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description CMPPS xmm1, xmm2/mem128, imm8 0F C2 /r ib Compares four pairs of packed single-precision floating-point values in an XMM register and an XMM register or 64-bit memory location. . xmm1 127 96 95 64 63 32 31 0 . xmm2/mem128 127 96 95 64 63 32 31 0 . . imm8 7 0 . . compare compare all 1s or 0s all 1s or 0s cmpps.eps Some compare operations that are not directly supported by the immediate-byte encodings can be implemented by swapping the contents of the source and destination operands and then executing the appropriate compare instruction using the swapped values. These additional compare operations are shown in Table 1-1 on CMPPS 27
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