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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point Exception, #XF Invalid-operation exception (IE) Denormalized-operand exception (DE) X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions X X X A source operand was an SNaN value. X X X A source operand was a denormal value. 80 CVTSS2SD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CVTSS2SI Convert Scalar Single-Precision Floating-Point to Signed Doubleword or Quadword Integer The CVTSS2SI instruction converts a single-precision floating-point value in the loworder 32 bits of an XMM register or a 32-bit memory location to a 32-bit or 64-bit signed integer value and writes the converted value in a general-purpose register. Mnemonic Opcode Description CVTSS2SI reg32, xmm2/mem32 F3 0F 2D /r Converts a single-precision floating-point value in an XMM register or 32-bit memory location to a doubleword integer value in a general-purpose register. CVTSS2SI reg64, xmm2/mem32 F3 0F 2D /r Converts a single-precision floating-point value in an XMM register or 32-bit memory location to a quadword integer value in a general-purpose register. reg32 xmm2/mem32 31 0 127 32 31 0 convert reg64 xmm2/mem32 63 0 127 32 31 0 convert with REX prefix cvtss2si.eps If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 – 1) or quadword value (–2 63 to +2 63 – 1), the instruction returns the indefinite integer value (8000_0000h for 32-bit integers, CVTSS2SI 81
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