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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PMULUDQ Packed Multiply Unsigned Doubleword and Store Quadword Multiplies two pairs of 32-bit unsigned integer values in the first and second source operands and writes the two 64-bit results in the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. The source operands are in the first (low-order) and third doublewords of the source operands, and the result of each multiply is stored in the first and second quadwords of the destination XMM register. Mnemonic Opcode Description PMULUDQ xmm1, xmm2/mem128 66 0F F4 /r Multiplies two pairs of 32-bit unsigned integer values in an XMM register and another XMM register or 128-bit memory location and writes the two 64-bit results in the destination XMM register. xmm1 xmm2/mem128 127 96 95 64 63 32 31 0 127 96 95 64 63 32 31 0 multiply multiply pmuludq-128.eps Related Instructions PMADDWD, PMULHUW, PMULHW, PMULLW rFLAGS Affected None MXCSR Flags Affected None 270 PMULUDQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PMULUDQ 271
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