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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 SHUFPD Shuffle Packed Double-Precision Floating-Point Moves either of the two packed double-precision floating-point values in the first source operand to the low-order quadword of the destination (first source) and moves either of the two packed double-precision floating-point values in the second source operand to the high-order quadword of the destination. In each case, the value of the destination quadword is determined by the least-significant two bits in the immediate-byte operand, as shown in Table 1-7. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description SHUFPD xmm1, xmm2/mem128, imm8 66 0F C6 /r ib Shuffles packed double-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and puts the result in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 64 63 0 imm8 7 0 mux mux shufpd.eps 350 SHUFPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Table 1-7. Immediate-Byte Operand Encoding for SHUFPD Destination Bits Filled Immediate-Byte Bit Field Value of Bit Field Source 1 Bits Moved Source 2 Bits Moved 63–0 0 127–64 1 0 63–0 — 1 127–64 — 0 — 63–0 1 — 127–64 Related Instructions SHUFPS rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. SHUFPD 351
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