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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 298 PSRAW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PSRLD Packed Shift Right Logical Doublewords Right-shifts each of the packed 32-bit values in the first source operand by the number of bits specified in the second source operand and writes each shifted value in the corresponding doubleword of the destination (first source). The first source/destination and second source operands are: „ an XMM register and another XMM register or 128-bit memory location, or „ an XMM register and an immediate byte value. The high-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greater than 31, the destination is cleared to 0. Mnemonic Opcode Description PSRLD xmm1, xmm2/mem128 66 0F D2 /r Right-shifts packed doublewords in an XMM register by the amount specified in the low 64 bits of an XMM register or 128- bit memory location. PSRLD xmm, imm8 66 0F 72 /2 ib Right-shifts packed doublewords in an XMM register by the amount specified in an immediate byte value. . xmm1 127 96 95 64 63 32 31 0 . xmm2/mem128 127 64 63 0 shift right . . shift right . xmm 127 96 95 64 63 32 31 0 . imm8 7 0 shift right . . shift right psrld-128.eps PSRLD 299
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