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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1; and the AMD extensions to MMX are not supported, as indicated by bit 22 of CPUID extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 234 PAVGW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PCMPEQB Packed Compare Equal Bytes Compares corresponding packed bytes in the first and second source operands and writes the result of each comparison in the corresponding byte of the destination (first source). For each pair of bytes, if the values are equal, the result is all 1s. If the values are not equal, the result is all 0s. The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PCMPEQB xmm1, xmm2/mem128 66 0F 74 /r Compares packed bytes in an XMM register and an XMM register or 128-bit memory location. xmm1 xmm2/mem128 . . . . . . . . . . . . . . 127 0 127 0 . . . . . . . . . . . . . . compare all 1s or 0s . . . . . . . . . . . . . . compare all 1s or 0s pcmpeqb-128.eps Related Instructions PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW rFLAGS Affected None MXCSR Flags Affected None PCMPEQB 235
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