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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indcated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned-memory reference was performed while alignment checking was enabled. 152 MOVDQU
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVHLPS Move Packed Single-Precision Floating-Point High to Low Moves two packed single-precision floating-point values from the high-order 64 bits of an XMM register to the low-order 64 bits of another XMM register. The high-order 64 bits of the destination XMM register are not modified. Mnemonic Opcode Description MOVHLPS xmm1, xmm2 0F 12 /r Moves two packed single-precision floating-point values from an XMM register to the destination XMM register. xmm1 xmm2 127 64 63 32 31 0 127 96 95 64 63 0 copy copy movhlps.eps Related Instructions MOVAPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPS rFLAGS Affected None MXCSR Flags Affected None MOVHLPS 153
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