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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions CMPPD, CMPPS, CMPSD, CMPSS, COMISD, UCOMISD, UCOMISS rFLAGS Affected ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF MXCSR Flags Affected 0 0 M 0 M M 21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0 Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated. FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. 40 COMISS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exception General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical.. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point Exception, #XF Invalid-operation exception (IE) Denormalized-operand exception (DE) Real Virtual 8086 Protected Cause of Exception X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions X X X A source operand was an SNaN or QNaN value. X X X A source operand was a denormal value. COMISS 41
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