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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. Device not available, #NM X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. 168 MOVMSKPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVNTDQ Move Non-Temporal Double Quadword Stores a 128-bit (double quadword) XMM register value into a 128-bit memory location. This instruction indicates to the processor that the data is non-temporal, and is unlikely to be used again soon. The processor treats the store as a write-combining (WC) memory write, which minimizes cache pollution. The exact method by which cache pollution is minimized depends on the hardware implementation of the instruction. For further information, see “Memory Optimization” in Volume 1. MOVNTDQ is weakly-ordered with respect to other instructions that operate on memory. Software should use an SFENCE instruction to force strong memory ordering of MOVNTDQ with respect to other stores. Mnemonic Opcode Description MOVNTDQ mem128, xmm 66 0F E7 /r Stores a 128-bit XMM register value into a 128-bit memory location, minimizing cache pollution. mem128 xmm 127 0 127 0 copy movntdq.eps Related Instructions MOVNTI, MOVNTPD, MOVNTPS, MOVNTQ rFLAGS Affected None MXCSR Flags Affected None MOVNTDQ 169
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