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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 218 PADDSB
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PADDSW Packed Add Signed with Saturation Words Adds each packed 16-bit signed integer value in the first source operand to the corresponding packed 16-bit signed integer in the second source operand and writes the signed integer result of each addition in the corresponding word of the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PADDSW xmm1, xmm2/mem128 66 0F ED /r Adds packed 16-bit signed integer values in an XMM register and another XMM register or 128-bit memory location and writes the result in the destination XMM register. xmm1 . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 xmm2/mem128 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 add saturate . . . . . . add saturate . . . . . . paddsw-128.eps For each packed value in the destination, if the value is larger than the largest representable signed 16-bit integer, it is saturated to 7FFFh, and if the value is smaller than the smallest signed 16-bit integer, it is saturated to 8000h. Related Instructions PADDB, PADDD, PADDQ, PADDSB, PADDUSB, PADDUSW, PADDW rFLAGS Affected None MXCSR Flags Affected None PADDSW 219
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