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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (CR0.EM) was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (CR4.OSFXSR) was cleared to 0. Device not available, X X X The task-switch bit (CR0.TS) was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X X A null data segment was used to reference memory. The destination operand was in a non-writable segment. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from executing the instruction. 170 MOVNTDQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVNTPD Move Non-Temporal Packed Double-Precision Floating-Point Stores two double-precision floating-point XMM register values into a 128-bit memory location. This instruction indicates to the processor that the data is non-temporal, and is unlikely to be used again soon. The processor treats the store as a write-combining (WC) memory write, which minimizes cache pollution. The exact method by which cache pollution is minimized depends on the hardware implementation of the instruction. For further information, see “Memory Optimization” in Volume 1. Mnemonic Opcode Description MOVNTPD mem128, xmm 66 0F 2B /r Stores two packed double-precision floating-point XMM register values into a 128-bit memory location, minimizing cache pollution. mem128 xmm 127 64 63 0 127 64 63 0 copy copy movntpd.eps MOVNTPD is weakly-ordered with respect to other instructions that operate on memory. Software should use an SFENCE instruction to force strong memory ordering of MOVNTPD with respect to other stores. Related Instructions MOVNTDQ, MOVNTI, MOVNTPS, MOVNTQ rFLAGS Affected None MXCSR Flags Affected None MOVNTPD 171
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